T/RTECHNOLOGICAL REFINEMENT CATALOG ↗
TRE COMPUTING / DEVELOPMENT PROGRAM

RYE CORE∞

One core.
Every scale.

The physical and software foundation beneath RYE-powered products. One intelligence architecture—built to inhabit everything from a sensor to a humanoid to a private intelligence server.

Explore the architecture First Core / RC-M1
ONECOREARCHITECTURE
μEMBEDDED
SEDGE
MPERSONAL
LPHYSICAL
XSOVEREIGN
SCROLL TO DESCEND
01 / CORE DEFINITION

Not only a motherboard.
A complete intelligence platform.

RYE CORE gives a device local intelligence, perception, memory, networking and the ability to participate in the RYE ecosystem. Different processors can carry the same identity, APIs, security model and software DNA.

COMPUTE+SECURE IDENTITY+RYE RUNTIME+MODEL RUNTIME+SENSOR I/O+NETWORK+MEMORY+SAFETY
02 / THE CORE FAMILY

One architecture.
Five envelopes.

Hardware changes with the application. The software model stays coherent. Each class has a clear power and capability envelope without locking TRE to one processor vendor.

CORE μ

Embedded Intelligence

Sensing, preprocessing, classification and local response for compact devices.

POWER
~2–10 W
ROLE
Sensors · modules · joints
CORE S

Edge Intelligence

Vision, speech, sensor fusion and local agents for connected edge systems.

POWER
~7–30 W
ROLE
Cameras · drones · portable
CORE MFIRST

Personal Intelligence

A meaningful local RYE for TR 01—even when the server is disconnected.

POWER
~20–80 W
ROLE
TR 01 · terminals
CORE L

Physical Intelligence

Perception, mission planning and embodied memory for machines that move.

POWER
~40–150 W
ROLE
TR 02 · TR 03 · robotics
CORE X

Sovereign Compute

Large models, simulation, training and private infrastructure at maximum scale.

POWER
~150 W+
ROLE
ASTRA · servers · simulation

Power ranges are engineering targets—not fixed final specifications.

03 / SHARED DNA

Different body.
Same intelligence.

Every Core exposes capabilities instead of assuming a specific device. Applications ask what the machine can do; the runtime decides where and how the work runs.

HARDWARESYSTEMRYE
COMPUTECPU / GPU / NPUMemory · storage · powerPHYSICAL FOUNDATION
CORE OSDrivers · secure bootUpdates · telemetrySYSTEM FOUNDATION
RYE RUNTIMEModels · memory · toolsEvents · device APIsINTELLIGENCE LAYER
NETWORKTR VPNTSAR Network · WORLDCONNECTED FOUNDATION
CAPABILITY MODEL

Ask what it can do.

CAN SPEAK? ✓CAN SEE? ✓CAN RUN LLM? ✓CAN MOVE? —CAN CONNECT? ✓CAN SIMULATE? —
ONE API

Stable above hardware.

rye.think()
rye.see()
rye.listen()
rye.speak()
rye.remember()
rye.act()
rye.world()
rye.network()
04 / DISTRIBUTED INTELLIGENCE

One mission.
Many Cores.

A RYE request runs locally when the device has the capability. If not, the runtime can route it to a nearby Core or to ASTRA. The intelligence spans compute classes without making the edge dependent on the cloud.

LOCAL MODEL?→NEARBY CORE?→ASTRA
EXAMPLE MISSION“Inspect the garage.”
  1. CORE MTR 01 understands the objective
  2. CORE LTR 02 navigates the environment
  3. CORE SCamera processes local vision
  4. WORLDEnvironment model is updated
  5. CORE XASTRA performs heavy analysis
  6. RYEOne coherent result returns
05 / MODULAR HARDWARE

Build products,
not motherboards.

A standardized Core module carries intelligence. Product-specific carrier boards provide cameras, audio, motors and power. The compute module can evolve without redesigning the entire machine.

STANDARDIZEDRYE CORE MODULE
↓
RYE CORE BUSHIGH-SPEED CONNECTOR

PCIe · USB · Ethernet · MIPI CSI · I²C · SPI · UART · CAN-FD · GPIO · Audio · Power · Debug

↓
TR EYE
VISIONTR EAR
AUDIOTR LINK
NETWORKTR SENSE
ENVIRONMENTTR DRIVE
MOTIONTR POWER
ENERGY
06 / PHYSICAL SAFETY

Intelligence plans.
Safety remains deterministic.

RYE never directly controls every motor cycle. Large models provide intent, perception, prediction and planning. Dedicated real-time controllers own balance, braking and actuator safety.

AI cannot override immutable hardware safety limits.
INTELLIGENCERYE / VISION / PLANNINGMission + intent
↓
MOTIONREAL-TIME CONTROLLERDeterministic control
↓
IMMUTABLESAFETY CONTROLLERLimits · E-stop · watchdog
↓
PHYSICALACTUATORSMotors + mechanisms
07 / ENGINEERING LAWS

Private. Resilient.
Replaceable underneath.

The system must keep essential local functions alive, verify every trusted layer and remain portable across present and future compute suppliers.

01

Graceful degradation

If ASTRA, the internet or TSAR Network disappears, essential local intelligence continues.

02

Root of trust

Hardware identity, secure boot, encrypted keys, attestation, signed updates and recovery.

03

Hardware abstraction

RYE CORE does not equal one vendor: NVIDIA, AMD, ARM, NPUs and future TRE silicon remain replaceable.

04

Energy intelligence

Thermals and battery state reshape workload while preserving navigation, safety and essential functions.

THE FIRST REAL RYE CORE

RC-M1

CORE M
DEV 01

Built to prove TR 01.

The first Core is not five boards at once. It is one credible personal intelligence module designed around measured model, I/O, thermal and power requirements.

16–32 GB+ RAM classNVMe storageWi-Fi / Bluetooth2.5 GbE targetUSB-CCamera + audioCAN-FD + GPIOSecure elementHardware watchdogQuiet cooling
MISSION / PROVE
  • Offline RYE
  • Voice + vision
  • Local memory + models
  • Device control
  • Server sync
  • TSAR Network
  • ASTRA offload
  • Secure updates
08 / DEVELOPMENT SEQUENCE

Architecture first.
Silicon last.

Prove the system with mature platforms, then own progressively more of the carrier, module and silicon only when the scale justifies it.

  1. 01Software specificationDefine runtime, identity, capabilities and APIs.
  2. 02CORE M dev kitBuild the common development foundation.
  3. 03TR 01Ship the first complete RYE CORE product.
  4. 04CORE SExtend vision and embedded intelligence.
  5. 05CORE LProve physical intelligence in TR 02.
  6. 06Distributed bodyScale toward TR 03 and custom modules.
RYE CORE / MODULAR INTELLIGENCE ARCHITECTURE

From a sensor to a humanoid
to a private intelligence server—
the same RYE architecture scales with the machine.

Do not build one computer for every application. Build one intelligence architecture that can inhabit many computers.

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